This invention is in the field of semiconductor integrated circuit manufacturing, and is more specifically directed to the fabrication of metallization conductor layers according to damascene processes.
In the field of integrated circuit manufacturing, a fundamental goal is to design and manufacture integrated circuits that are as small as possible. As is well known in this art, the manufacturing cost of an integrated circuit corresponds strongly to the wafer area occupied by each integrated circuit die or chip. This is because the chip area correlates directly to the number of possible integrated circuits per manufactured wafer, and because the theoretical yield, for a given manufacturing defect density, increases as chip area decreases. In addition, the smaller feature sizes that result in decreasing chip area provide improved device performance and increased functionality per unit area.
An important advance that has reduced the necessary chip area for modern integrated circuits is the technology for forming multiple levels of metal conductors. Increases in the number of available metal levels has provided dramatic reduction in chip area and increased device and functionality density.
Of course, the implementation of multiple metal levels presents many challenges and tradeoffs. The cross-sectional area of each metal conductor is preferably minimized, especially in the lower levels, to permit overlying levels to make connections to lower metal levels and to underlying active devices. These narrower-pitch metal lines require high resolution photolithography. In addition, because current density increases with decreasing conductor cross-sectional area, the vulnerability of the finished conductors to electromigration is increased for these narrow pitch conductors. Another rule pertains to the aspect (height-to-width) ratio between metal layers. These factors affect the selection of materials and fabrication methods for modern integrated circuit metallization.
Copper has become a popular metallization material in modern integrated circuits, replacing aluminum in many instances. Copper is significantly more conductive than aluminum, and is also less vulnerable to electromigration failure than aluminum. In modern processes, because of the difficulty of chemically etching copper metal, damascene processes are often used to form multiple levels of copper conductors. In general, damascene processes refer to the inlaying of a metal into etched grooves or trenches that define the conductor lines. In contrast, traditional metallization is formed by the depositing of a metal layer over insulating films on the wafer surface, followed by the patterned etching of the metal film to define the conductors.
According to conventional “single damascene” processes, vias are etched through an interlevel insulating film at locations at which the conductor is to contact underlying elements, which may be portions of active semiconductor devices or metal conductors in previous levels. The vias are then filled with metal, such as copper, typically by electrochemical deposition (e.g., electroplating). Another conductive material, such as tungsten or aluminum, may also be used to fill the vias. Chemical-mechanical polishing (CMP) is then performed to remove excess copper (or other conductive material) from the surface of the insulator, leaving the conductor inlaid within the vias. An intrametal insulator layer is then deposited over the structure, and trenches are etched through the intrametal insulator layer at those locations at which the conductors are to run laterally along the surface of the device. The trenches are generally etched to expose the top of the filled vias to allow contact to the underlying elements through the vias. Copper metal is then deposited overall, again typically by electroplating. After deposition, the copper is planarized (e.g., by CMP) to leave the conductors in this level inlaid into the intrametal insulating film. The via and trench damascene process may be repeated for additional metal levels in the integrated circuit structure, with as many as eight levels being formed in modern manufacturing processes.
Dual damascene copper metal processes refer to metallization systems in which both the trenches and vias are simultaneously filled with the copper metallization. “Trench first” dual damascene processes refer to those processes in which trenches are etched into the insulator before the vias are etched, while “via first” processes define and etch the vias prior to trench etch. In either case, copper metal is simultaneously deposited into the trenches and vias, typically by electrochemical deposition (e.g., electroplating). The damascene inlay is then completed by CMP of the structure.
In both single and dual damascene processes, the use of a cap layer to overlie the insulating layers is known. These cap layers serve to protect the surface of the insulating layer during via and trench etches. This protection is especially important in those processes in which the interlevel and intrametal insulating layers are formed of low dielectric constant materials, such as organosilicate glass (OSG). In this case, the cap layer remains in place under the patterned photoresist, and protects the OSG film from punchthrough by the etch if the photoresist is partially or fully eroded during the etch, or during subsequent etches such as those used to clear etch-stop layers at via bottoms. This cap layer is also referred to as a hardmask layer, considering that the layer assists in defining the locations of trenches and vias.
By way of further background, silicon nitride is a known cap layer material in damascene processes. Examples of silicon nitride cap layers at various stages of damascene processes are described in U.S. Pat. No. 6,424,044, U.S. Pat. No. 6,127,258, and U.S. Pat. No. 6,465,340.
It has been observed, in connection with this invention, that the use of a silicon nitride cap layer is less than optimal in modern damascene processes, especially in defining extremely small vias. FIGS. 1a through 1c illustrate an example of a conventional via etch, as used in connection with a conventional damascene metal process. In this example, referring first to FIG. 1a, underlying conductor 2 is disposed within an insulating layer 1; for example, conductor 2 may be a copper conductor in a lower damascene metal level, or alternatively may be a semiconductor element such as a diffused region or a transistor gate. In any event, active semiconductor elements, such as transistors and passive components, are present within or beneath insulating layer 1, in the conventional manner. Etch-stop layer 3, typically formed of silicon carbide, is disposed over conductor 2, and low dielectric constant (“low-k”, or “ultra-low-k”) insulator layer 4 is disposed over etch-stop layer 3. In modern processes, insulator layer 4 is often formed of an OSG material, examples of which include BLACK DIAMOND silicon oxide-based CVD low-k film available from Applied Materials, Inc.; CORAL low-k dielectric film available from Novellus Systems Inc.; and SiLK dielectric material available from Dow Chemical Co. Examples of ultra-low-k materials include ORION 2.2 ultra-low-k dielectric material available from Trikon Technologies, Inc.; BLACK DIAMOND 2 insulator material available from Applied Materials, Inc.; p-SiLK dielectric material available from Dow Chemical Co.; and LKD-5109 low-k dielectric material available from JSR Corporation. Typically, insulator layer 4 is deposited using CVD techniques, although spin-on techniques may also be used. Silicon nitride cap layer 5 overlies insulator layer 4, as shown in FIG. 1a. The photolithographic patterning of the location of a via to be etched through insulator layer 4 is defined by patterned photoresist 6, which is photolithographically exposed and developed in the conventional manner, in combination with bottom antireflective coating (BARC) layer 7, which is disposed under photoresist 6 as shown.
FIG. 1b illustrates the structure of FIG. 1a, following a conventional via etch through low-k insulating layer 4, using photoresist 6 as a mask. This etch is a conventional plasma etch, with active species selected according to the material of insulating layer 4, as known in the art. Residue 6′ remains at the surface, and consists of remaining portions of photoresist 6 and BARC layer 7. Following this etch process, etch-stop layer 3 is exposed at the bottom of the via. Because the material of etch-stop layer 3 (e.g., silicon carbide) is resistant to the via etch, it remains substantially intact at this point. However, as evident from FIG. 1a, silicon nitride cap layer 5 is not completely impervious to the via etch. Rather, cap layer 5 may be etched, or eroded, in a lateral direction due to its lower etch resistance; as a result, the via critical dimension (CD) will widen (increase). This undesirable widening of the via through insulating layer 4 continues with the clearing of etch-stop layer 3 from the bottom of the via; despite the selection of an etchant species and condition that is suitable for etching etch-stop layer 3, silicon nitride cap layer 5 will be further laterally etched, so that it and the underlying portions of insulating layer 4 that are exposed after cap layer 5 pulls back are both etched. The resulting via in FIG. 1c is thus significantly wider than the via dimensions defined by the patterning of photoresist 6 (FIG. 1a). By way of example, this CD increase may be as much as on the order of 30 nm in via width, for a via having a desired width of 140 nm, resulting in a CD increase of on the order of 20%.
This widening of the via dimensions is typically referred to as CD increase, referring to an increase of the critical dimension of the via width. In modern processes, via width is a critical dimension, particularly in repetitive structures such as memory arrays, because the size and spacing of the etched vias largely determine the density of the conductors in the current metal level, and may indirectly also define the density of the underlying structures 2.
However, because the via width is a critical dimension that defines the overall density of conductors and contacts in a given level, the photolithography process used in defining via locations is likely to be pushed to its manufacturable limits. For example, in modern processes, so-called “193 nm” photolithography, using exposure wavelengths at least as short as 193 nm, are used to define via locations. Because the via photolithography process is already at its limits, especially at 193 nm or lower wavelengths, the via pattern cannot be adjusted by undersizing the vias further, to account for the CD increase, during via etch and etch-stop layer etch, using the silicon nitride cap layer. Rather, the integrated circuit design rules must be loosened to allow for the widened vias.
By way of further background, silicon carbide is also a known material for use as the cap layer in damascene processes. An example of this use of a silicon carbide cap layer is described in U.S. Pat. No. 6,472,333. Referring to FIG. 1a, according to this conventional approach, silicon carbide would serve as cap layer 5.
However, it has been observed, in connection with this invention, that the via etch process using silicon carbide as a cap layer is vulnerable to the failure mechanism that is commonly referred to as “resist poisoning”. Low-k and ultra-low-k films, such as insulating film 4 in FIG. 1a, are relatively porous materials. Nitrogen-containing materials are typically used in preceding processes, including CMP and surface pretreatment prior to etch-stop layer deposition. This nitrogen, either as an amine or in the form of ammonia, tends to be trapped in residue from the CMP process. These contaminants infiltrate the OSG film and remain within the pores. The slurry used in CMP is especially likely to provide this infiltrating nitrogen, in the form of ammonia or amine. Once the nitrogen contaminant is present in insulating film 4, it has a tendency to outgas from the film in later processes, such as trench or via pattern in a single damascene copper metal process. The deleterious effect of the nitrogen is often seen in photolithography operations that use chemically-amplified positive photoresists, such as is common in the 193 nm photoresists used for critical dimension patterns. Chemically-amplified photoresists, as known in the art, rely upon a photo-acid-based chemical reaction to transfer the exposure pattern through the complete depth of the photoresist layer, from the surface locations that were exposed to the UV light energy. However, at those locations at which nitrogen has outgassed, the acid-based reaction will stop upon reaching the basic (i.e., the amine) contaminant. This incomplete exposure of the photoresist layer at these locations, which will be at the vias in via patterning, will cause a killing physical defect, namely a missing via. It has been observed, in connection with this invention, that silicon carbide is a poor barrier to the outgassed nitrogen or ammonia, leaving the via process vulnerable to this failure mechanism.